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command interface 4m-bit ma rom with expansion i/o hf88m04 preliminary product specification product nam e com m a nd interface 4m-bit mask rom with expansion i/o kb doc. no. hf88m04.doc kb product. no. hf88m04 - t a ble of contents ? 1 function description ............................................................................................ 2 2 featur es ................................................................................................................. 2 3 functional block diagram .................................................................................... 3 pin description .............................................................................................................. 4 4.1 pad location ............................................................................................. 5 4.2 pad coordination ..................................................................................... 6 5 device operation ................................................................................................... 7 5.1 retrieve data in data file........................................................................ 9 5.2 loading the addr ess counter ................................................................. 9 5.3 sequential read mode and auto incr ement of addr ess counter ..... 10 5.4 output data to extern al i/o.................................................................. 10 5.5 reading input pin status ....................................................................... 10 5.6 retrieving the contents of expansion i/o r e gisters ........................... 1 1 6 t iming dia g rams ................................................................................................ 1 1 6.1 data file read cycle ............................................................................. 1 1 6.2 interrupted by i/o w h e n loading addr ess counter .......................... 1 1 6.3 setting and reading the i/o mode for p0 and p1............................... 12 6.4 reading p0 and p1 in mixed-i/o mode ............................................... 12 6.5 reading the input pins ........................................................................... 13 6.6 output to p 0 and p1 .............................................................................. 13 7 absolute maximum rating ................................................................................. 14 8 ac electrical characteristics ............................................................................. 14 -1 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 9 dc electrical characteristics ............................................................................. 15 10 application cir c uit diagram .......................................................................... 15 1 function description the hf88m04 is a comm and interfaced 512 k x 8 bit mask rom. it features command mode interface with ex ternal cpu or mcu. in other wo rd s, it u s es on ly 8-bit data bus and a few additional control pins to load addresses and provide the rom access as well as expansion i/o ports cap ability . this design not only reduces pin count required to access da ta in rom dra m atically but also allows for system s expansion to higher capacity m e mories while using the existing board design. the application areas include voice, graphic, data storage in consum er product. 2 features data file mode with only 1 1 pin interface sixteen-bit expansion i/o pins with three-state m ode v o ltage range 2.4v ~ 5.5v -2 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 9 or ganization - mem o ry cell array: 512k x 8 9 sequential read operation in data file operation mode - sequential access : 120ns (m in.) at v dd = 5.0v 9 com m a nd/address/data multiplexed i/o port 9 low operation current (t ypical) - 10 3 functional block diagram me mo r y ce l l ar r a y se n s e am p . oe n x buf f e r & de c o de r [d 7 . . d 0 ] co n t ro l l ogi c y buf f e r & de c o de r ce n [ p 00. . p 0 7] [ p 10. . p 1 7] [ a c 1 8. . a 0] ac 0 ac 1 ac 2 p0 d i r 0 p1 d i r 1 we n rs 2 . . r s 0 -3 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 4 pin description h f 88 m 0 4- plc c 3 2 11 2 9 8 7 6 5 4 29 28 24 27 3 30 31 2 23 25 13 14 15 18 19 20 21 22 32 16 1 12 17 26 p01 p02 p03 p04 p05 p06 p07 p14 p16 p15 oe p10 p17 rs 1 rs 2 rs 0 p12 p13 d0 d1 d2 d4 d5 d6 d7 ce vd d vss we p00 d3 p11 s y m b o l p i n n o . i / o d e s c r i p t i o n vdd 32 p positive power supply input pin. v s s 1 6 p g o u n d p i n . cen 22 i the cen (chip enable) i nput is the device selection and power control for in ternal ma sk rom array . whenever cen goes high, the internal mask r o m will enter standby (power saving) m ode and accesse s to internal registers are inhibited. otherwise, it is in a c tive m ode and the contents of the rom and regis t ers can be acces sed. please note that only accesses to th e inte rnal registers are inhibited, but the status of i/o registers are not af fected by the cen pin and will rem a in unchanged. cen is also useful to uniquely select a certain device for app lica tion s where m u ltiple-chip array is required. w e n 1 i wen controls writing to internal regis t ers su ch as the output port registers, di rection registers, address counter and data on d7 ~ d0 are latched on the rising edge of the we pulse. the we n (w rite enable) inpu t is internally pulled-up to vdd to pre v ent pin floating. so this pin sho u ld stay at ?1? state when inactive to prevent unintended current consum ption. o e n 24 i oen (output enable) is the output control which gates rom array data, expansion i/ o ports, direction registers to the data i/o pins d7 ~ d0. the interna l addres s counter will autom a tically increm e n t by one with each rising edge of oen pin in sequentially read m ode. rs2~rs0 i register select p i ns rs2 ~ rs0 for acces sing r o m data, address counter , as well as expansion i/o ports. -4 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 p17 ~ p10 i/o bi-directional i/o port p1. p07 ~ p00 i/o bi-directional i/o port p0. d7 ~ d0 21 ~ 17, 15 ~13 io the bi-direc tional data i / o pi ns are used to input starting address, setting the expansi on i/o direction and output registers, and to output ro m array data during read operations, contents of i/o re gisters and status of input pins. the d 7 ~ d7 float to high-im pedance when the chip is deselected (cen high) or when the outputs are disabled. 4.1 pad location p16 p15 p10 p11 p13 p12 d7 d6 d5 d4 d3 d2 d1 d0 p00 p01 p02 p03 nc nc nc nc p04 p05 p06 p07 p14 p17 wen vdd vdd vdd rs2 rs1 rs0 oen cen vss vss vss -5 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 4.2 pad coordination pad num b er pad nam e x coordinate y coordinate 1 p 0 7 1 0 8 . 3 3 2 4 3 1 . 7 5 2 p 0 6 1 0 8 . 3 3 2 2 4 4 . 3 1 3 p 0 5 1 0 8 . 3 3 2 0 5 7 . 0 3 4 p 0 4 1 0 8 . 3 3 1 8 6 9 . 5 9 5 n c 1 0 8 . 3 3 1 6 8 2 . 3 6 6 n c 1 0 8 . 3 3 1 4 9 4 . 9 2 7 n c 1 0 8 . 3 3 1 3 0 7 . 7 4 8 n c 1 0 8 . 3 3 1 1 1 9 . 3 4 9 p 0 3 1 0 8 . 3 3 9 3 2 . 1 7 1 0 p 0 2 1 0 8 . 3 3 7 4 4 . 7 3 1 1 p 0 1 1 0 8 . 3 3 5 5 7 . 4 5 1 2 p 0 0 1 0 8 . 3 3 3 7 0 . 0 1 1 3 d 0 1 0 8 . 3 3 1 8 2 . 7 2 1 4 d 1 3 9 5 . 9 7 1 0 9 . 1 4 1 5 d 2 5 8 3 . 1 3 1 0 9 . 1 4 1 6 g n d 9 9 7 . 3 9 2 2 0 . 7 1 1 7 g n d 1 2 4 2 . 3 4 1 4 0 . 9 1 1 8 g n d 1 5 2 1 . 3 8 1 0 8 . 0 9 1 9 d 3 1 6 8 4 . 0 2 1 0 9 . 1 4 2 0 d 4 1 8 7 1 . 1 8 1 0 9 . 1 4 2 1 d 5 2 0 5 8 . 6 2 1 0 9 . 1 4 2 2 d 6 2 2 4 5 . 7 8 1 0 9 . 1 4 2 3 d 7 2 7 4 5 . 8 7 1 0 5 . 7 9 2 4 c e n 2 7 4 5 . 8 7 2 2 9 . 5 5 2 5 p 1 2 2 7 4 5 . 8 7 3 5 5 . 1 7 2 6 o e n 2 7 4 5 . 8 7 4 8 0 . 3 2 2 7 p 1 3 2 7 5 9 . 4 8 1 3 6 5 . 8 3 2 8 p 1 1 2 7 5 9 . 4 8 1 4 9 1 . 7 4 2 9 p 1 0 2 7 5 9 . 4 8 1 6 1 7 . 6 3 3 0 p 1 5 2 7 4 8 . 8 7 2 4 2 7 . 9 2 3 1 p 1 6 2 7 4 8 . 8 7 2 5 5 5 . 1 3 3 2 r s 1 2 1 0 7 . 6 6 2 5 6 6 . 9 2 3 3 r s 2 1 9 2 0 . 2 2 2 5 6 6 . 9 2 3 4 v d d 1 5 7 8 . 7 6 2 5 1 3 . 7 2 3 5 v d d 1 4 0 4 . 3 4 2 5 1 3 . 7 2 3 6 v d d 1 2 2 9 . 9 2 2 5 1 3 . 7 2 3 7 w e n 1 0 2 9 . 2 3 2 5 5 2 . 3 -6 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 3 8 r s 0 8 4 1 . 1 9 2 5 5 2 . 3 3 9 p 1 7 4 9 5 . 5 7 2 5 5 2 . 3 4 0 p 1 4 3 0 8 . 1 3 2 5 5 2 . 3 5 device operation the device provides the capability of access i ng the contents of rom array by external mcu not through standard address and data bus confi guration but through m i ni m a l number of 8-bit data bus and control pins. only 1 1 pins d7 ~ d0, cen, oen, wen a r e required to use the device as a data file device. by fixing the rs2 to ?0?, only cen, w e n, oen and d0 ~ d7 are required to access the rom array data. the cen pin is device selection pin to unique ly select one d e vice when more than o n e device are used in parallel and control the acces s to mask rom contents and intern al regis t ers. w h enever cen goes hig h, the inte r n al mask rom will enter s t and b y (power sav i ng) m ode and acces ses to internal registers are inhibited. otherwise, it is in activ e mode. therefore, when access i ng contents of rom is not intended, cen should stay at ?1? to conserve the power . in addition to data file mode, the device also provide the expansion i/o capability . t w o ports of i/o pins (8 bit each) are provided. the i/o ports can be configured to function as output pin or high-im pedance i nput pins. only 14 pins, cen, w e n, oen, rs2, rs1 a nd d0 ~ d7 are required to provi de the data f i le function and full access to two i/o ports. there are se ven intern al regis t ers us e d to provide the f unction a lity of data f ile as well as expansion i/o capability . these regi sters are selected by rs2 ~ rs0. all registers are 8-bit wide except ac2. ac2 ~ ac0 are write-only and constitute th e com p lete 19-bit address counter used as pointer to the data. w h ile the p0, p1, dir0 and dir1 can be read as well as writt en. their initia l values a r e as indica ted in the following table. w h en rs2 = ?0?, the rs1 ~ rs0 are ignored, the address counter can be loaded or cont ents of data file can be read. this is to reduce the required pin needed for external mc u to in terf a ce with the devi ce and also s i m p lify the procedure for loading the address counter . the p0, p1, dir0, and dir1 are used for e xpansion i/o registers. the p0 and p1 -7 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 are output registers of expans ion i/o and dir0 and dir1 are the direction registers that determ ine the i/o mode of p0 and p1. each pin can be configured as output or input m ode indiv i dually by setting or re settin g the corres ponding pin of the dir registers. initially , both p0 and p1 are default to input m ode at ?hi? state. dir 0 0 r s = 1 00 & oe n = ' 0 ' r s = 1 01 & oe n = ' 0 ' r s = 1 11 & oe n = ' 0 ' r s = 1 10 & oe n = ' 0 ' p0 0 d0 p1 0 1 0 qd qd p0 0 di r 0 0 1 0 q d di r 1 0 q p1 0 d the accesse s to the in te rnal regis t ers will be in hibited whe n cen is ?1?. however , the sta t us of interna l reg i ste r s, such as expansio n i/o ports, will not be a f f ected. for exam ple, if a certa in pin is in output m ode and driving ?hi?, it will no t c h ange when cen pin goes to ?1? state. therefore, the us ers are advised to take care of the power down condition of i/o ports when entering sleep m ode to prevent unnecessary pow er drain. rs 2 rs 1 rs 0 s y m b o l t y p e d e s c r i p t i o n initial v a l u e r read data by indirect access ac2 w address latch 2 for a18 ~ a16 ?--------? ac1 w address latch 1 for a15 ~ a8 ?--------? 0xx ac0 w address latch 0 for a7 ~ a0 ?--------? 100 p0 r/w port 0 output register ? 11111111 ? 101 dir0 r/w direction register 0 ?00000000? 11 0 p 1 r / w p o r t 1 o u t p u t r e g i s t e r ? 11111111 ? 1 1 1 dir1 r/w direction register 0 ?00000000? -8 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 5.1 retrieve data in data file accesses to the rom contents, expansi on i/o, address counter and direction registers are m a de through 8 data i/o pins ? d7 ~ d0. w ith register s e lection rs = ?0xx?, the starting addresses can be writt en through data i/os by bringing wen to low and back to high. addresses are latched on the rising edge of w e n. once the starting address of data block is latched into the address counter , data m a y be read out by sequentially pul sing oen with cen staying lo w . w h en at ?0?, th e oen gate the data of the selected address unt o data i/o pin d7 ~ d0. w i th the rising edge of oen, the internal address counter is increm ented by one autom a tically . 5.2 loading the addr ess counter before the data can be retr ieved, the address counter m u st be initialized with the starting address, then the contents of ro m point ed to by address counter (ac) can be accessed through d7 through d0. in orde r to sim p lify the procedure of loading 19-bit address counter (ac), a internal point er is im ple m ented and used to point to next reg i ste r to write in the up to three - cycle address loading sequence. initially , with rs = ?0xx? cen goes from ?1? to ?0? and the ac pointer is initialized. the pointer is th en increm ented to poin t to next reg i ste r with f a lling edg e o f each w e n pulse. so when random ly accessing data within a 256-byte page, or within a 64k-byte block m ode, t h en only one or two-cy cle address reload process is needed to access dif f erent locations within a page or block. the address counter pointer will be held in reset state in the following conditions: 1. w h en cen is ' 1 ' (the device is deselected). 2. by the read pulse (oen is ' 0 ' ) and rs2 = ' 0 ' (rom is being accesses). the inclus io n of the 3rd condition is to f o r ce th e address load ing to s t ar t f r om lsb of address co unter once the read cycle is initia ted . however , the ac pointer will no t be rese t when reading or writing f r om /to expansion i/o registers (p0, p1, dir0, dir1). this design is useful in certain applica tion scen arios where in the m i dst of the m u lti-by te address loading process, an interrupt to the mcu m a in loop occurs. and in the inte rrup t s e rvice rou t ine, m a nipulation of expansi on i/o registers is perform e d, i.e., key board is scanned using p0 and p1. w h en the execution of -9 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 program returns to m a in loop after interrupt service routine com p leted, the loading of address can still resum e f r om where it was interrupted. 5.3 sequential read mode and auto incr ement of addr ess counter w ith each read access to th e rom data (r s = ?0xx?), the a ddress counter is increm ented autom a tically by one with ris i ng edge of oen to facility sequential access to a block of rom data and avoid repeated loading of addresses. 5.4 output data to external i/o the device ? s 16-bit expansion i / o capability provides a dditiona l i / o ports f o r applications where the i/o pin are h eavily us ed. t o use as a certa in pin as output pin, the corr espo nding bit in direction register m u st be set to ?1?. plea se ref e r to the following exam ple where output 0x00 to p0 to ?0? is intended. 1. set rs to ?101? (dir0). 2. keep d7 ~ d0 at 0xf f (all bits in output m ode). 3. pulse the w e n to low then high to write to write contents of d-bus to dir0. 4. set rs to ?100? (p0 output register). 5. set d7 ~ d0 to 0x00. 6. pulse the w e n to low then high to write con t en ts of d-bus to p0 and d r ive all bits in p0 to low . 5.5 reading input pin status t o use expansion i/o ports as input pins an d read the status fro m them , the corresponding bit in direction register m u st be set to ?0?. please see the following exam ple where reading inputs from of p1 is intended. 1. set rs to ?1 1 1 ? (dir1). 2. set d7 ~ d0 to 0x00. 3. pulse the w e n to low then high to set dir1 to all high-im pedance input m ode. 4. set rs to ?1 10? (p1 output register). 5. pulse the oen to low . 6. read p1 then set the oen back to high. there is one thing should be noted. for any unused (open) e xpansion i/o pin, it is advisable to set the port to out put mode either at ?0 ? or ?1 ? sta t e to prevent it from -1 0- 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 floating or fix it at vdd or vss i f it is se t to input m ode . otherwise, the noise m i ght cause the unnecessary power consum ption. 5.6 retrieving the contents of expansion i/o r e gisters the contents of all four registers can be r ead through data bus. th e ability to access the contents of registers avoids the necessi ty of using the ram as m i rror to keep the current status of latches in applications. however , extra care should be taken when reading p0 and p1. t o read the contents of p0 and p1, the dir0 and dir1 should be set to outpu t m ode. otherwise, th e pin s t atu s inste a d of p0 and p1 will be read . the sam e precaution sh ould be app lied in read-modify-w rite sequence that read back the contents of the output register of output m ode pins and i nput status of input m ode pins. 6 timing diagrams 6.1 data file read cycle 6.2 interrupted by i/o w h en loading addr ess counter -1 1 - 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 6.3 setting and reading the i/o mode for p0 and p1 6.4 reading p0 and p1 in mixed-i/o mode -1 2- 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 6.5 reading the input pins 6.6 output to p0 and p1 -1 3- 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 7 absolute maximum rating item s s y m b o l r a t i n g c o n d i t i o n supply v o ltage v dd -0.3 to 6 v input v o ltage v in -0.3 to vdd+0.3 v operating t e m p erature t opr -5 to 70 8 ac electrical characteristics read cycle there are two ways of access i ng th e rom data. the first one is to ass e rt the valid address on the address bus, then assert ce n ?low? to enab le th e rom array . the access tim e in th is m ode is sp ecified as t ace . t h e advantage of this acc ess m ode is that power consum ption can be lowered. the second access m ode keeps the cen ?low? while changes the addres ses to acces s the conten ts of rom data. the acces s tim e in this way is sp ecif i ed as t aa . in this device, th e address access t i me decrease monotonically w ith increasing voltage, and it is shorter than chip enable access t i m e when th e operation v o ltage is higher then 4.5 v . therefore in v op -1 4- 10/ 17/ 01
command interface 4m-bit ma rom with expansion i/o hf88m04 higher th an 4.5 v o lts, it is m o re advisable to use the address access mod e to achiev e faster access to rom data when the power consum ption is not a concern. i t e m s y m b o l 2 . 4 v 3.0 v 3 . 3 v 3 . 6 v 4 . 5 v 5 . 0 v 5 . 5 v uni t r e m a r k chip enable access t i m e t ace 2 8 0 1 9 0 1 7 0 1 5 0 1 5 0 1 9 0 2 1 0 n s m i n address access t i m e t aa 2 4 0 2 1 0 2 1 0 2 1 0 2 0 0 1 9 0 1 8 0 n s m i n 9 dc electrical characteristics (v ss = 0v , v dd = 5.0 v , t op r = 25 10 application circuit diagram this application circuit illu strates th at how kb83760 mcu uses two external HF88M04S for rom expansion as well as key board scan functions. -1 5- 10/ 17/ 01
vd d vd d vd d v d d vd d u2 h f 88m 04- plc c 3 2 11 2 9 8 7 6 5 4 29 28 24 27 3 30 31 2 23 25 13 14 15 18 19 20 21 22 32 16 1 12 17 26 p01 p02 p03 p04 p05 p06 p07 p14 p16 p15 oe p10 p17 rs 1 rs 2 rs 0 p12 p13 d0 d1 d2 d4 d5 d6 d7 ce vd d vss we p00 d3 p11 u3 h f 88m 04- plc c 3 2 11 2 9 8 7 6 5 4 29 28 24 27 3 30 31 2 23 25 13 14 15 18 19 20 21 22 32 16 1 12 17 26 p01 p02 p03 p04 p05 p06 p07 p14 p16 p15 oe p10 p17 rs 1 rs 2 rs 0 p12 p13 d0 d1 d2 d4 d5 d6 d7 ce vd d vss we p00 d3 p11 r2 330 k r3 330 k r4 330 k r5 330 k u1 kb8376 0 72 73 134 130 131 132 133 16 17 18 19 142 143 144 97 98 99 100 64 63 62 61 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 71 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 122 123 124 125 126 127 128 129 11 10 15 14 13 12 141 140 139 138 22 21 20 85 84 76 93 92 87 86 96 8 9 81 82 83 88 89 90 91 94 95 137 136 135 41 42 43 65 66 67 68 69 70 74 75 77 78 79 80 117 118 119 120 121 1 2 3 4 5 6 7 38 39 40 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 seg42 seg41 lv2 co m 0 lc 1 lc 2 lv1 co m 2 9 co m 3 0 co m 3 1 seg95 gn d vo da o seg17 seg16 seg15 seg14 seg50 seg51 seg52 seg53 seg91 seg90 seg89 seg88 seg87 seg86 seg85 seg84 seg83 seg82 seg81 seg80 seg79 seg78 seg77 seg70 seg69 seg68 seg67 seg66 seg65 seg64 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg43 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 co m 1 5 co m 1 4 co m 8 co m 7 co m 6 co m 5 co m 4 co m 3 co m 2 co m 1 co m 2 4 co m 2 3 co m 2 8 co m 2 7 co m 2 6 co m 2 5 lvg lr 0 lr 1 lr 2 seg92 seg93 seg94 seg29 seg30 seg38 seg21 seg22 seg27 seg28 seg18 co m 2 1 co m 2 2 seg33 seg32 seg31 seg26 seg25 seg24 seg23 seg20 seg19 lr 3 lr 4 lv3 seg73 seg72 seg71 set 49 seg48 seg47 seg46 seg45 seg44 seg40 seg39 seg37 seg36 seg35 seg34 co m 1 3 co m 1 2 co m 1 1 co m 1 0 co m 9 pw m p pw m n co m 1 6 co m 1 7 co m 1 8 co m 1 9 co m 2 0 seg76 seg75 seg74 opi n opi p opo rs tp fx o fx i ts tp sxo sxi vd d mu t e dtm f o sd o keyt on e pr t d 7 pr t d 6 pr t d 5 pr t d 4 pr t d 3 pr t d 2 pr t d 1 pr t d 0 pr t c 7 pr t c 6 pr t c 5 pr t c 4 pr t c 3 pr t c 2 pr t c 1 pr t c 0 pr t 107 pr t 106 pr t 105 pr t 104 pr t 103 pr t 102 pr t 101 pr t 100 pr t 117 pr t 116 pr t 115 pr t 114 pr t 113 pr t 112 pr t 111 pr t 110 c1 1uf c1 0 1uf c2 1uf c3 1uf c4 1uf c5 1uf c6 1uf c7 1uf c8 1uf c9 1uf d1 1n 4148 2 1 d2 1n 4148 2 1 d3 1n 4148 2 1 d4 1n 4148 2 1 d5 1n 4148 2 1 d6 1n 4148 2 1 d7 1n 4148 2 1 k1 k2 r1 330 k k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 k14 k15 k16 k17 k18 k19 k20 k21 k22 k23 k24 k25 k26 k27 k28 k29 k30 k31 k32 k33 k34 k35 pause 5 erase name hold m7 auto down up 6 *# 4 1 8 m10 m1 2 mute 7 hf m6 flash pgm dial m2 m9 m5 0 3 m4 9m redial m3 command interface 4m-bit ma rom with expansion i/o hf88m04 -1 6- 10/ 17/ 01 c7 c6 r1 seg65 p r t1 1 0 c5 r2 seg64 p r t1 1 1 c4 r4 seg63 pr t 112 c 3 oen o en seg62 p r t1 1 3 c2 r3 seg61 pr t 114 c 1 c e 1n c e 2n seg60 p r t1 1 5 d0 d7 d0 d7 seg59 pr t 116 seg58 pr t 117 seg57 pr t 100 seg56 pr t 101 seg55 pr t 102 seg54 pr t 103 seg53 pr t 104 seg52 pr t 105 seg51 pr t 106 seg50 pr t 107 seg49 rs 0 seg48 rs 1 seg47 rs 2 c 7 seg46 oen c 6 seg45 we n c 5 seg44 ce 1 n c4 seg43 ce 2 n c3 seg42 c2 seg41 d0 c1 seg40 d1 seg39 d2 seg38 d3 seg37 d4 seg36 d5 seg35 d6 seg34 d7 seg33 kt on e seg32 sd o seg31 dtm f o r 1 seg30 mu t e seg29 seg28 sxi seg27 sxo seg26 ts tp seg25 fx i r 2 seg24 fx o seg23 rs tp seg22 opo seg21 opi p seg20 opi n seg19 da o r 3 r4 vo r5 seg66 seg18 seg67 seg17 seg68 seg16 seg69 seg15 seg70 seg14 seg71 seg13 seg72 seg12 seg73 seg11 seg74 seg10 seg75 seg9 seg76 seg8 seg77 seg7 seg78 seg6 seg79 seg5 seg80 seg4 seg81 seg3 seg82 seg2 seg83 seg1 seg84 seg0 seg85 co m 1 5 seg86 co m 1 4 seg87 co m 1 3 seg88 co m 1 2 seg89 co m 1 1 seg90 co m 1 0 seg91 co m 9 seg92 co m 8 seg93 co m 7 seg94 co m 6 seg95 co m 5 co m 3 1 co m 4 co m 3 0 co m 3 co m 2 9 co m 2 co m 2 8 co m 1 co m 2 7 co m 0 co m 2 6 co m 2 5 co m 2 4 co m 2 3 co m 2 2 co m 2 1 co m 2 0 co m 1 9 co m 1 8 co m 1 7 co m 1 6 pw m n pw m p r5 d1 d2 rs 0 we n d 3 d4 rs 2 d 5 rs 1 d 6 d1 d2 rs 0 we n d 3 d4 rs 2 d 5 rs 1 d 6 8

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